As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, techniques are developed to achieve greater storage capacity. Compared to a planar transistor structure, a vertical structure of the 3D NAND memory devices is involved with more complex manufacturing processes. As the 3D NAND memory devices migrates to configurations with more memory cell layers to achieve higher densities at a lower cost per bit, it becomes an increasing challenge to improve structures and methods for manufacturing the same.